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| PRELIMINARY CY7C1366C CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM Features * Supports bus operation up to 225 MHz * Available speed grades are 225, 200 and 166 MHz * Registered inputs and outputs for pipelined operation *Optimal for performance (Double-Cycle deselect) --Depth expansion without wait state *3.3V -5% and +10% core power supply (VDD) * 2.5V / 3.3V I/O operation * Fast clock-to-output times -- 2.8 ns (for 225-MHz device) -- 3.0 ns (for 200-MHz device) -- 3.5 ns (for 166-MHz device) * Provide high-performance 3-1-1-1 access rate * User-selectable burst counter supporting Intel Pentium interleaved or linear burst sequences * Separate processor and controller address strobes * Synchronous self-timed writes * Asynchronous output enable * Available in Lead-Free 100 TQFP,119 BGA and 165 fBGA packages * IEEE 1149.1 JTAG-Compatible Boundary Scan * "ZZ" Sleep Mode Option Functional Description[1] The CY7C1366C/CY7C1367C SRAM integrates 262,144 x 36 and 524,288 x 18 SRAM cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE1), depth-expansion Chip Enables (CE2 and CE3[2]), Burst Control inputs (ADSC, ADSP, and ADV), Write Enables (BWX, and BWE), and Global Write (GW). Asynchronous inputs include the Output Enable (OE) and the ZZ pin. Addresses and chip enables are registered at rising edge of clock when either Address Strobe Processor (ADSP) or Address Strobe Controller (ADSC) are active. Subsequent burst addresses can be internally generated as controlled by the Advance pin (ADV). Address, data inputs, and write controls are registered on-chip to initiate a self-timed Write cycle.This part supports Byte Write operations (see Pin Descriptions and Truth Table for further details). Write cycles can be one to four bytes wide as controlled by the byte write control inputs. GW active LOW causes all bytes to be written. This device incorporates an additional pipelined enable register which delays turning off the output buffers an additional cycle when a deselect is executed.This feature allows depth expansion without penalizing system performance. The CY7C1366C/CY7C1367C operates from a +3.3V core power supply while all outputs operate with a +3.3V or a +2.5V supply. All inputs and outputs are JEDEC-standard JESD8-5-compatible. 225 MHz 200 MHz 3.0 220 30 166 MHz 3.5 180 30 Unit ns mA mA Selection Guide Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 2.8 250 30 Shaded areas contain advance information. Please contact your local Cypress sales representative for availability of these parts. Notes: 1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com. 2. CE3 is for TQFP and 165 fBGA package only. 119 BGA is offered only in 2 Chip Enable. Cypress Semiconductor Corporation Document #: 38-05542 Rev. *A * 3901 North First Street * San Jose, CA 95134 * 408-943-2600 Revised October 5, 2004 PRELIMINARY 1 CY7C1366C CY7C1367C Logic Block Diagram - CY7C1366C (256K x 36) A0,A1,A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK BURST LOGIC Q1 COUNTER AND CLR ADSC ADSP BWD DQD,DQPD BYTE WRITE REGISTER DQc,DQPC BYTE WRITE REGISTER DQB,DQPB BYTE WRITE REGISTER DQA,DQPA BYTE WRITE REGISTER ENABLE REGISTER Q0 DQD,DQPD BYTE WRITE DRIVER DQc,DQPC BYTE WRITE DRIVER DQB,DQPB BYTE WRITE DRIVER DQA,DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BWC OUTPUT REGISTERS OUTPUT BUFFERS E BWB DQs DQPA DQPB DQPC DQPD BWA BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL 2 Logic Block Diagram - CY7C1367C (512K x 18) A0, A1, A ADDRESS REGISTER 2 A[1:0] MODE ADV CLK Q1 BURST COUNTER AND LOGIC CLR Q0 ADSC ADSP DQB, DQPB BYTE WRITE REGISTER DQA , DQPA BYTE WRITE REGISTER ENABLE REGISTER DQB , DQPB BYTE WRITE DRIVER DQA, DQPA BYTE WRITE DRIVER MEMORY ARRAY SENSE AMPS BWB OUTPUT REGISTERS OUTPUT BUFFERS E DQs, DQPA DQPB BWA BWE GW CE1 CE2 CE3 OE PIPELINED ENABLE INPUT REGISTERS ZZ SLEEP CONTROL Document #: 38-05542 Rev. *A Page 2 of 27 PRELIMINARY Pin Configurations 100-pin TQFP Pinout (3 Chip Enables) A A CE1 CE2 BWD BWC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A CY7C1366C CY7C1367C 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 DQPC DQC DQC VDDQ VSSQ DQC DQC DQC DQC VSSQ VDDQ DQC DQC NC VDD NC VSS DQD DQD VDDQ VSSQ DQD DQD DQD DQD VSSQ VDDQ DQD DQD DQPD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1366C (256K X 36) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPB DQB DQB VDDQ VSSQ DQB DQB DQB DQB VSSQ VDDQ DQB DQB VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA DQA DQA VSSQ VDDQ DQA DQA DQPA NC NC NC VDDQ VSSQ NC NC DQB DQB VSSQ VDDQ DQB DQB NC VDD NC VSS DQB DQB VDDQ VSSQ DQB DQB DQPB NC VSSQ VDDQ NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 A A CE1 CE2 NC NC BWB BWA CE3 VDD VSS CLK GW BWE OE ADSC ADSP ADV A A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 CY7C1367C (512K x 18) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 A NC NC VDDQ VSSQ NC DQPA DQA DQA VSSQ VDDQ DQA DQA VSS NC VDD ZZ DQA DQA VDDQ VSSQ DQA DQA NC NC VSSQ VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A Document #: 38-05542 Rev. *A MODE A A A A A1 A0 NC / 72M NC / 36M VSS VDD NC / 18M A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Page 3 of 27 PRELIMINARY Pin Configurations (continued) 119-ball BGA (2 Chip Enable with JTAG) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQC DQC VDDQ DQC DQC VDDQ DQD DQD VDDQ DQD DQD NC NC VDDQ 2 A CE2 A DQPC DQC DQC DQC DQC VDD DQD DQD DQD DQD DQPD A NC TMS CY7C1366C (256K x 36) 3 4 5 A A ADSP A A VSS VSS VSS BWC VSS NC VSS BWD VSS VSS VSS MODE A TDI ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD A TCK A A VSS VSS VSS BWB VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPB DQB DQB DQB DQB VDD DQA DQA DQA DQA DQPA A NC NC 7 VDDQ NC NC DQB DQB VDDQ DQB DQB VDDQ DQA DQA VDDQ DQA DQA NC ZZ VDDQ CY7C1366C CY7C1367C CY7C1367C (512K x 18) 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQB NC VDDQ NC DQB VDDQ NC DQB VDDQ DQB NC NC NC VDDQ 2 A CE2 A NC DQB NC DQB NC VDD DQB NC DQB NC DQPB A A TMS 3 A A A VSS VSS VSS BWB VSS NC VSS VSS VSS VSS VSS MODE A TDI 4 ADSP ADSC VDD NC CE1 OE ADV GW VDD CLK NC BWE A1 A0 VDD NC TCK 5 A A A VSS VSS VSS VSS VSS NC VSS BWA VSS VSS VSS NC A TDO 6 A A A DQPA NC DQA NC DQA VDD NC DQA NC DQA NC A A NC 7 VDDQ NC NC NC DQA VDDQ DQA NC VDDQ DQA NC VDDQ NC DQA NC ZZ VDDQ Document #: 38-05542 Rev. *A Page 4 of 27 PRELIMINARY Pin Configurations (continued) 165-ball fBGA (3 Chip Enable) CY7C1366C (256K x 36) CY7C1366C CY7C1367C 1 A B C D E F G H J K L M N P R NC / 288M NC DQPC DQC DQC DQC DQC NC DQD DQD DQD DQD DQPD NC MODE 2 A A NC DQC DQC DQC DQC VSS DQD DQD DQD DQD NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWC BWD VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 BWB BWA VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE VSS VDD 9 ADV ADSP 10 A A NC DQB DQB DQB DQB NC DQA DQA DQA DQA NC A A 11 NC NC / 144M DQPB DQB DQB DQB DQB ZZ DQA DQA DQA DQA DQPA A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC / 18M A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A VDD VDD VDD VDD VDD VDD VDD VDD VSS A A A CY7C1367C (512K x 18) 1 A B C D E F G H J K L M N P R NC / 288M NC NC NC NC NC NC NC DQB DQB DQB DQB DQPB NC MODE 2 A A NC DQB DQB DQB DQB VSS NC NC NC NC NC NC / 72M NC / 36M 3 CE1 CE2 VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 4 BWB NC VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A 5 NC BWA VSS VSS VSS VSS VSS VSS `VSS VSS VSS VSS NC TDI TMS 6 CE3 CLK 7 BWE GW 8 ADSC OE 9 ADV ADSP 10 A A NC NC NC NC NC NC DQA DQA DQA DQA NC A A 11 A NC / 144M DQPA DQA DQA DQA DQA ZZ NC NC NC NC NC A A VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC / 18M A1 A0 VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS NC TDO TCK VSS VDD VDD VDD VDD VDD VDD VDD VDD VDD VSS A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A A A Document #: 38-05542 Rev. *A Page 5 of 27 PRELIMINARY Pin Definitions Name A0, A1, A I/O InputSynchronous InputSynchronous InputSynchronous InputSynchronous InputClock InputSynchronous CY7C1366C CY7C1367C Description Address Inputs used to select one of the address locations. Sampled at the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 [2]are sampled active. A1: A0 are fed to the two-bit counter. Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes to the SRAM. Sampled on the rising edge of CLK. BWA,BWB BWC,BWD GW BWE CLK CE1 CE2 CE3[2] OE ADV ADSP ADSC ZZ DQs, DQPs VDD VSS VSSQ VDDQ MODE TDO Global Write Enable Input, active LOW. When asserted LOW on the rising edge of CLK, a global write is conducted (ALL bytes are written, regardless of the values on BWX and BWE). Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This signal must be asserted LOW to conduct a byte write. Clock Input. Used to capture all synchronous inputs to the device. Also used to increment the burst counter when ADV is asserted LOW, during a burst operation. Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if CE1 is HIGH. CE1 is sampled only when a new external address is loaded. InputChip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE3[2] to select/deselect the device.CE2 is sampled only when a new external address is loaded. InputChip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction Synchronous with CE1 and CE2 to select/deselect the device.Not connected for BGA. Where referenced, CE3[2] is assumed active throughout this document for BGA. CE3 is sampled only when a new external address is loaded. InputOutput Enable, asynchronous input, active LOW. Controls the direction of the I/O pins. When Asynchronous LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ pins are three-stated, and act as input data pins. OE is masked during the first clock of a read cycle when emerging from a deselected state. InputAdvance Input signal, sampled on the rising edge of CLK, active LOW. When asserted, it Synchronous automatically increments the address in a burst cycle. InputAddress Strobe from Processor, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH. InputAddress Strobe from Controller, sampled on the rising edge of CLK, active LOW. When Synchronous asserted LOW, addresses presented to the device are captured in the address registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both asserted, only ADSP is recognized. InputZZ "sleep" Input, active HIGH. When asserted HIGH places the device in a non-time-critical Asynchronous "sleep" condition with data integrity preserved. For normal operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down. I/OBidirectional Data I/O lines. As inputs, they feed into an on-chip data register that is triggered Synchronous by the rising edge of CLK. As outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous clock rise of the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are placed in a three-state condition. Power Supply Power supply inputs to the core of the device. Ground Ground for the core of the device. I/O Ground Ground for the I/O circuitry. I/O Power Supply Power supply for the I/O circuitry. InputSelects Burst Order. When tied to GND selects linear burst sequence. When tied to VDD or left floating selects interleaved burst sequence. This is a strap pin and should remain static Static during device operation. Mode Pin has an internal pull-up. JTAG serial output Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the JTAG Synchronous feature is not being utilized, this pin should be disconnected. This pin is not available on TQFP packages. Document #: 38-05542 Rev. *A Page 6 of 27 PRELIMINARY Pin Definitions (continued) Name TDI CY7C1366C CY7C1367C TMS TCK NC I/O Description JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAG serial input Serial data-In to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature is Synchronous not being utilized, this pin can be disconnected or connected to VDD. This pin is not available on TQFP packages. JTAGClock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must be Clock connected to VSS. This pin is not available on TQFP packages. - No Connects. Not internally connected to the die. Single Write Accesses Initiated by ADSP This access is initiated when both of the following conditions are satisfied at clock rise: (1) ADSP is asserted LOW, and (2) chip select is asserted active. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The write signals (GW, BWE, and BWX) and ADV inputs are ignored during this first cycle. ADSP triggered write accesses require two clock cycles to complete. If GW is asserted LOW on the second clock rise, the data presented to the DQx inputs is written into the corresponding address location in the memory core. If GW is HIGH, then the write operation is controlled by BWE and BWX signals. The CY7C1366C/CY7C1367C provides byte write capability that is described in the Write Cycle Description table. Asserting the Byte Write Enable input (BWE) with the selected Byte Write input will selectively write to only the desired bytes. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1366C/CY7C1367C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQ inputs. Doing so will three-state the output drivers. As a safety precaution, DQ are automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Single Write Accesses Initiated by ADSC ADSC write accesses are initiated when the following conditions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted HIGH, (3) chip select is asserted active, and (4) the appropriate combination of the write inputs (GW, BWE, and BWX) are asserted active to conduct a write to the desired byte(s). ADSC triggered write accesses require a single clock cycle to complete. The address presented is loaded into the address register and the address advancement logic while being delivered to the memory core. The ADV input is ignored during this cycle. If a global write is conducted, the data presented to the DQX is written into the corresponding address location in the memory core. If a byte write is conducted, only the selected bytes are written. Bytes not selected during a byte write operation will remain unaltered. A synchronous self-timed write mechanism has been provided to simplify the write operations. Because the CY7C1366C/CY7C1367C is a common I/O device, the Output Enable (OE) must be deasserted HIGH before presenting data to the DQX inputs. Doing so will three-state the output drivers. As a safety precaution, DQX are Functional Overview All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The CY7C1366C/CY7C1367C supports secondary cache in systems utilizing either a linear or interleaved burst sequence. The interleaved burst order supports Pentium and i486 processors. The linear burst sequence is suited for processors that utilize a linear burst sequence. The burst order is user selectable, and is determined by sampling the MODE input. Accesses can be initiated with either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC). Address advancement through the burst sequence is controlled by the ADV input. A two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the Byte Write Enable (BWE) and Byte Write Select (BWX) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are simplified with on-chip synchronous self-timed write circuitry. Synchronous Chip Selects CE1, CE2, CE3[2] and an asynchronous Output Enable (OE) provide for easy bank selection and output three-state control. ADSP is ignored if CE1 is HIGH. Single Read Accesses This access is initiated when the following conditions are satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2) chip selects are all asserted active, and (3) the write signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1 is HIGH. The address presented to the address inputs is stored into the address advancement logic and the Address Register while being presented to the memory core. The corresponding data is allowed to propagate to the input of the Output Registers. At the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within tco if OE is active LOW. The only exception occurs when the SRAM is emerging from a deselected state to a selected state, its outputs are always three-stated during the first cycle of the access. After the first cycle of the access, the outputs are controlled by the OE signal. Consecutive single read cycles are supported. The CY7C1366C/CY7C1367C is a double-cycle deselect part. Once the SRAM is deselected at clock rise by the chip select and either ADSP or ADSC signals, its output will three-state immediately after the next clock rise. Document #: 38-05542 Rev. *A Page 7 of 27 PRELIMINARY automatically three-stated whenever a write cycle is detected, regardless of the state of OE. Burst Sequences The CY7C1366C/CY7C1367C provides a two-bit wraparound counter, fed by A[1:0], that implements either an interleaved or linear burst sequence. The interleaved burst sequence is designed specifically to support Intel(R) Pentium applications. The linear burst sequence is designed to support processors that follow a linear burst sequence. The burst sequence is user selectable through the MODE input. Both read and write burst operations are supported. Asserting ADV LOW at clock rise will automatically increment the burst counter to the next address in the burst sequence. Both read and write burst operations are supported. Sleep Mode The ZZ input pin is an asynchronous input. Asserting ZZ places the SRAM in a power conservation "sleep" mode. Two clock cycles are required to enter into or exit from this "sleep" mode. While in this mode, data integrity is guaranteed. Accesses pending when entering the "sleep" mode are not considered valid nor is the completion of the operation guaranteed. The device must be deselected prior to entering the "sleep" mode. CEs, ADSP, and ADSC must remain inactive for the duration of tZZREC after the ZZ input returns LOW. CY7C1366C CY7C1367C Interleaved Burst Address Table (MODE = Floating or VDD) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 00 11 10 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 10 01 00 Linear Burst Address Table (MODE = GND) First Address A1: A0 00 01 10 11 Second Address A1: A0 01 10 11 00 Third Address A1: A0 10 11 00 01 Fourth Address A1: A0 11 00 01 10 Partial Truth Table for Read/Write[5, 10] Function (CY7C1366C) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write Bytes B, A Write Byte C - (DQC and DQPC) Write Bytes C, A Write Bytes C, B Write Bytes C, B, A Write Byte D - (DQD and DQPD) Write Bytes D, A Write Bytes D, B Write Bytes D, B, A Write Bytes D, C Write Bytes D, C, A Write Bytes D, C, B Write All Bytes Write All Bytes Truth Table for Read/Write[5, 10] Function (CY7C1367C) Read Read Write Byte A - (DQA and DQPA) Write Byte B - (DQB and DQPB) Write All Bytes Write All Bytes Document #: 38-05542 Rev. *A GW H H H H H H H H H H H H H H H H H L BWE H L L L L L L L L L L L L L L L L X GW H H H H H L BWD X H H H H H H H H L L L L L L L L X BWE H L L L L X BWC X H H H H L L L L H H H H L L L L X BWB X H H L L X BWB X H H L L H H L L H H L L H H L L X BWA X H L H L H L H L H L H L H L H L X BWA X H L H L X Page 8 of 27 PRELIMINARY IEEE 1149.1 Serial Boundary Scan (JTAG) The CY7C1366C/CY7C1367C incorporates a serial boundary scan test access port (TAP)in the BGA package only. The TQFP package does not offer this functionality. This part operates in accordance with IEEE Standard 1149.1-1900, but doesn't have the set of functions required for full 1149.1 compliance. These functions from the IEEE specification are excluded because their inclusion places an added delay in the critical speed path of the SRAM. Note the TAP controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant TAPs. The TAP operates using JEDEC-standard 3.3V or 2.5V I/O logic levels. The CY7C1366C/CY7C1367C contains a TAP controller, instruction register, boundary scan register, bypass register, and ID register. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be unconnected. They may alternately be connected to VDD through a pull-up resistor. TDO should be left unconnected. Upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. Test MODE SELECT (TMS) CY7C1366C CY7C1367C The TMS input is used to give commands to the TAP controller and is sampled on the rising edge of TCK. It is allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. Test Data-In (TDI) The TDI ball is used to serially input information into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is chosen by the instruction that is loaded into the TAP instruction register. For information on loading the instruction register, see Figure . TDI is internally pulled up and can be unconnected if the TAP is unused in an application. TDI is connected to the most significant bit (MSB) of any register. (See Tap Controller Block Diagram.) Test Data-Out (TDO) The TDO output ball is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. The output changes on the falling edge of TCK. TDO is connected to the least significant bit (LSB) of any register. (See Tap Controller State Diagram.) TAP Controller Block Diagram 0 Bypass Register 210 TAP Controller State Diagram 1 TEST-LOGIC RESET 0 0 RUN-TEST/ IDLE 1 SELECT DR-SCAN 0 1 CAPTURE-DR 0 SHIFT-DR 1 EXIT1-DR 0 PAUSE-DR 1 0 EXIT2-DR 1 UPDATE-DR 1 0 0 0 1 0 1 1 SELECT IR-SCAN 0 CAPTURE-IR 0 SHIFT-IR 1 EXIT1-IR 0 PAUSE-IR 1 EXIT2-IR 1 UPDATE-IR 1 0 0 1 0 1 TDI Selection Circuitry Instruction Register 31 30 29 . . . 2 1 0 Selection Circuitry TDO Identification Register x. . . . .210 Boundary Scan Register TCK TMS TAP CONTROLLER Performing a TAP Reset A RESET is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. This RESET does not affect the operation of the SRAM and may be performed while the SRAM is operating. At power-up, the TAP is reset internally to ensure that TDO comes up in a High-Z state. The 0/1 next to each state represents the value of TMS at the rising edge of TCK. Test Access Port (TAP) Test Clock (TCK) The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. TAP Registers Registers are connected between the TDI and TDO balls and allow data to be scanned into and out of the SRAM test circuitry. Only one register can be selected at a time through the instruction register. Data is serially loaded into the TDI ball on the rising edge of TCK. Data is output on the TDO ball on the falling edge of TCK. Document #: 38-05542 Rev. *A Page 9 of 27 PRELIMINARY Instruction Register Three-bit instructions can be serially loaded into the instruction register. This register is loaded when it is placed between the TDI and TDO balls as shown in the Tap Controller Block Diagram. Upon power-up, the instruction register is loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a reset state as described in the previous section. When the TAP controller is in the Capture-IR state, the two least significant bits are loaded with a binary "01" pattern to allow for fault isolation of the board-level serial test data path. Bypass Register To save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS instruction is executed. Boundary Scan Register The boundary scan register is connected to all the input and bidirectional balls on the SRAM. The boundary scan register is loaded with the contents of the RAM I/O ring when the TAP controller is in the Capture-DR state and is then placed between the TDI and TDO balls when the controller is moved to the Shift-DR state. The EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can be used to capture the contents of the I/O ring. The Boundary Scan Order tables show the order in which the bits are connected. Each bit corresponds to one of the bumps on the SRAM package. The MSB of the register is connected to TDI and the LSB is connected to TDO. Identification (ID) Register The ID register is loaded with a vendor-specific, 32-bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out when the TAP controller is in the Shift-DR state. The ID register has a vendor code and other information described in the Identification Register Definitions table. TAP Instruction Set Overview Eight different instructions are possible with the three-bit instruction register. All combinations are listed in the Instruction Codes table. Three of these instructions are listed as RESERVED and should not be used. The other five instructions are described in detail below. The TAP controller used in this SRAM is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. The TAP controller cannot be used to load address data or control signals into the SRAM and cannot preload the I/O buffers. The SRAM does not implement the 1149.1 commands EXTEST or INTEST or the PRELOAD portion of SAMPLE/PRELOAD; rather, it performs a capture of the I/O ring when these instructions are executed. CY7C1366C CY7C1367C Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST EXTEST is a mandatory 1149.1 instruction which is to be executed whenever the instruction register is loaded with all 0s. EXTEST is not implemented in this SRAM TAP controller, and therefore this device is not compliant to 1149.1. The TAP controller does recognize an all-0 instruction. When an EXTEST instruction is loaded into the instruction register, the SRAM responds as if a SAMPLE/PRELOAD instruction has been loaded. There is one difference between the two instructions. Unlike the SAMPLE/PRELOAD instruction, EXTEST places the SRAM outputs in a High-Z state. IDCODE The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register upon power-up or whenever the TAP controller is given a test logic reset state. SAMPLE Z The SAMPLE Z instruction causes the boundary scan register to be connected between the TDI and TDO balls when the TAP controller is in a Shift-DR state. It also places all SRAM outputs into a High-Z state. SAMPLE/PRELOAD SAMPLE / PRELOAD is a 1149.1 mandatory instruction. When the SAMPLE / PRELOAD instructions are loaded into the instruction register and the TAP controller is in the Capture-DR state, a snapshot of data on the inputs and output pins is captured in the boundary scan register. The user must be aware that the TAP controller clock can only operate at a frequency up to 20 MHz, while the SRAM clock operates more than an order of magnitude faster. Because there is a large difference in the clock frequencies, it is possible that during the Capture-DR state, an input or output will undergo a transition. The TAP may then try to capture a signal while in transition (metastable state). This will not harm the device, but there is no guarantee as to the value that will be captured. Repeatable results may not be possible. To guarantee that the boundary scan register will capture the correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller's capture set-up plus hold times (tCS and tCH). The SRAM clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a SAMPLE / PRELOAD instruction. If this is an issue, it is still possible to capture all other signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Document #: 38-05542 Rev. *A Page 10 of 27 PRELIMINARY Once the data is captured, it is possible to shift out the data by putting the TAP into the Shift-DR state. This places the boundary scan register between the TDI and TDO pins. PRELOAD allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. The shifting of data for the SAMPLE and PRELOAD phases can occur concurrently when required - that is, while data captured is shifted out, the preloaded data can be shifted in. BYPASS When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a Shift-DR state, the bypass CY7C1366C CY7C1367C register is placed between the TDI and TDO balls. The advantage of the BYPASS instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. Reserved These instructions are not implemented but are reserved for future use. Do not use these instructions. TAP Timing 1 Test Clock (TCK) t TMSS 2 3 4 5 6 t TH t TMSH t TL t CYC Test Mode Select (TMS) t TDIS t TDIH Test Data-In (TDI) t TDOV t TDOX Test Data-Out (TDO) DON'T CARE UNDEFINED TAP AC Switching Characteristics Over the operating Range[3, 4] Parameter Clock TCK Clock Cycle Time TCK Clock Frequency TCK Clock HIGH time TCK Clock LOW time Output Times TCK Clock LOW to TDO Valid TCK Clock LOW to TDO Invalid Setup Times TMS Set-Up to TCK Clock Rise TDI Set-Up to TCK Clock Rise Capture Set-Up to TCK Rise Hold Times TMS hold after TCK Clock Rise TDI Hold after Clock Rise Capture Hold after Clock Rise tTMSH tTDIH tCH 5 5 5 ns ns ns tTMSS tTDIS tCS 5 5 5 ns ns tTDOV tTDOX 0 5 ns ns tTCYC tTF tTH tTL 25 25 50 20 ns MHz ns ns Symbol Min Max Unit Document #: 38-05542 Rev. *A Page 11 of 27 PRELIMINARY TAP AC Switching Characteristics Over the operating Range[3, 4] Parameter Symbol Min CY7C1366C CY7C1367C Max Unit Notes: 3. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register. 4. Test conditions are specified using the load in TAP AC test Conditions. tR/tF = 1 ns. Document #: 38-05542 Rev. *A Page 12 of 27 PRELIMINARY 3.3V TAP AC Test Conditions Input pulse levels ....... ........................................VSS to 3.3V Input rise and fall times ...................... ..............................1ns Input timing reference levels ...........................................1.5V Output reference levels...................................................1.5V Test load termination supply voltage...............................1.5V CY7C1366C CY7C1367C 2.5V TAP AC Test Conditions Input pulse levels ........................................ VSS to 2.5V Input rise and fall time ......................................................1ns Input timing reference levels................... ......................1.25V Output reference levels .................. ..............................1.25V Test load termination supply voltage .................... ........1.25V 3.3V TAP AC Output Load Equivalent 1.5V 50 TDO Z O= 50 20pF 2.5V TAP AC Output Load Equivalent 1.25V 50 TDO Z O= 50 20pF TAP DC Electrical Characteristics And Operating Conditions (0C < TA < +70C; VDD = 3.3V 0.165V unless otherwise noted)[5] Parameter VOH1 VOH2 VOL1 VOL2 VIH VIL IX Description Output HIGH Voltage Output HIGH Voltage Output LOW Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Load Current GND < VIN < VDDQ IOH = -4.0 mA IOH = -1.0 mA IOH = -100 A IOL = 8.0 mA IOL = 8.0 mA IOL = 100 A Conditions VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V 2.0 1.7 -0.5 -0.3 -5 Min. 2.4 2.0 2.9 2.1 0.4 0.4 0.2 0.2 VDD + 0.3 VDD + 0.3 0.7 0.7 5 Max. Unit V V V V V V V V V V V V A Identification Register Definitions Instruction Field Revision Number (31:29) Device Depth (28:24)[6] Device Width (23:18) Cypress Device ID (17:12) Cypress JEDEC ID Code (11:1) ID Register Presence Indicator (0) CY7C1366C (256K x36) 000 01011 000110 100110 00000110100 1 CY7C1367C (512K x18) 000 01011 000110 010110 00000110100 1 Description Describes the version number. Reserved for Internal Use Defines memory type and architecture Defines width and density Allows unique identification of SRAM vendor. Indicates the presence of an ID register. Note: 5. All voltages referenced to VSS (GND). 6. Bit #24 is "1" in the Register Definitions for both 2.5v and 3.3v versions of this device. Document #: 38-05542 Rev. *A Page 13 of 27 PRELIMINARY Scan Register Sizes Register Name Instruction Bypass ID Boundary Scan Order (119-ball BGA package) Boundary Scan Order (165-ball fBGA package) Bit Size (x36) 3 1 32 71 71 CY7C1366C CY7C1367C Bit Size (x18) 3 1 32 71 71 Identification Codes Instruction EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS Code 000 001 010 011 100 101 110 111 Description Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM outputs to High-Z state. Loads the ID register with the vendor ID code and places the register between TDI and TDO. This operation does not affect SRAM operations. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Forces all SRAM output drivers to a High-Z state. Do Not Use: This instruction is reserved for future use. Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not affect SRAM operation. Do Not Use: This instruction is reserved for future use. Do Not Use: This instruction is reserved for future use. Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 119-Ball BGA Boundary Scan Order CY7C1366C (256K x 36) BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BALL ID K4 H4 M4 F4 B4 A4 G4 C3 B3 D6 H7 G6 E6 D7 E7 F6 G7 H6 Signal Name CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB DQB DQB DQB DQB DQB DQB BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 BALL ID P4 N4 R6 T5 T3 R2 R3 P2 P1 L2 K1 N2 N1 M2 L1 K2 Internal H1 Signal Name A0 A1 A A A A MODE DQPD DQD DQD DQD DQD DQD DQD DQD DQD Internal DQC BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 BALL ID K4 H4 M4 F4 B4 A4 G4 C3 B3 T2 Internal Internal Internal D6 E7 F6 G7 H6 CY7C1367C (512K x 18) Signal Name CLK GW BWE OE ADSC ADSP ADV A A A Internal Internal Internal DQPA DQA DQA DQA DQA BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 BALL ID P4 N4 R6 T5 T3 R2 R3 Internal Internal Internal Internal P2 N1 M2 L1 K2 Internal H1 Signal Name A0 A1 A A A A MODE Internal Internal Internal Internal DQPB DQB DQB DQB DQB Internal DQB Document #: 38-05542 Rev. *A Page 14 of 27 PRELIMINARY 119-Ball BGA Boundary Scan Order (continued) CY7C1366C (256K x 36) BIT# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID T7 K7 L6 N6 P7 N7 M6 L7 K6 P6 T4 A3 C5 B5 A5 C6 A6 B6 Signal Name ZZ DQA DQA DQA DQA DQA DQA DQA DQA DQPA A A A A A A A A BIT# 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 BALL ID G2 E2 D1 H2 G1 F2 E1 D2 C2 A2 E4 B2 L3 G3 G5 L5 Internal Signal Name DQC DQC DQC DQC DQC DQC DQC DQPC A A CE1 CE2 BWD BWC BWB BWA Internal BIT# 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID T7 K7 L6 N6 P7 Internal Internal Internal Internal Internal T6 A3 C5 B5 A5 C6 A6 B6 CY7C1366C CY7C1367C CY7C1367C (512K x 18) Signal Name ZZ DQA DQA DQA DQA Internal Internal Internal Internal Internal A A A A A A A A BIT# 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 BALL ID G2 E2 D1 Internal Internal Internal Internal Internal C2 A2 E4 B2 Internal Internal G3 L5 Internal Signal Name DQB DQB DQB Internal Internal Internal Internal Internal A A CE1 CE2 Internal Internal BWB BWA Internal 165-Ball fBGA Boundary Scan Order CY7C1366C (256K x 36) BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 BALL ID B6 B7 A7 B8 A8 B9 A9 B10 A10 C11 E10 F10 G10 D10 D11 E11 F11 Signal Name CLK GW BWE OE ADSC ADSP ADV A A DQPB DQB DQB DQB DQB DQB DQB DQB BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 BALL ID R6 P6 R4 P4 R3 P3 R1 N1 L2 K2 J2 M2 M1 L1 K1 J1 Internal Signal Name A0 A1 A A A A MODE DQPD DQD DQD DQD DQD DQD DQD DQD DQD Internal BIT# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 BALL ID B6 B7 A7 B8 A8 B9 A9 B10 A10 A11 Internal Internal Internal C11 D11 E11 F11 CY7C1367C (512K x 18) Signal Name CLK GW BWE OE ADSC ADSP ADV A A A Internal Internal Internal DQPA DQA DQA DQA BIT# 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 BALL ID R6 P6 R4 P4 R3 P3 R1 Internal Internal Internal Internal N1 M1 L1 K1 J1 Internal Signal Name A0 A1 A A A A MODE Internal Internal Internal Internal DQPB DQB DQB DQB DQB Internal Document #: 38-05542 Rev. *A Page 15 of 27 PRELIMINARY 165-Ball fBGA Boundary Scan Order (continued) CY7C1366C (256K x 36) BIT# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID G11 H11 J10 K10 L10 M10 J11 K11 L11 M11 N11 R11 R10 P10 R9 P9 R8 P8 P11 Signal Name DQB ZZ DQA DQA DQA DQA DQA DQA DQA DQA DQPA A A A A A A A A BIT# 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 BALL ID G2 F2 E2 D2 G1 F1 E1 D1 C1 B2 A2 A3 B3 B4 A4 A5 B5 A6 Signal Name DQC DQC DQC DQC DQC DQC DQC DQC DQPC A A CE1 CE2 BWD BWC BWB BWA CE3 BIT# 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 BALL ID G11 H11 J10 K10 L10 M10 Internal Internal Internal Internal Internal R11 R10 P10 R9 P9 R8 P8 P11 CY7C1366C CY7C1367C CY7C1367C (512K x 18) Signal Name DQA ZZ DQA DQA DQA DQA Internal Internal Internal Internal Internal A A A A A A A A BIT# 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 BALL ID G2 F2 E2 D2 Internal Internal Internal Internal Internal B2 A2 A3 B3 Internal Internal A4 B5 A6 Signal Name DQB DQB DQB DQB Internal Internal Internal Internal Internal A A CE1 CE2 Internal Internal BWB BWA CE3 Document #: 38-05542 Rev. *A Page 16 of 27 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage on VDD Relative to GND........ -0.5V to +4.6V DC Voltage Applied to Outputs in three-state ....................................... -0.5V to VDDQ + 0.5V DC Input Voltage....................................-0.5V to VDD + 0.5V CY7C1366C CY7C1367C Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage........................................... >2001V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... >200 mA Operating Range Range Commercial Industrial [7, 8] Ambient Temperature 0C to +70C VDD VDDQ 3.3V - 5%/+10% 2.5V - 5% to VDD -40C to +85C Electrical Characteristics Over the Operating Range Parameter VDD VDDQ VOH VOL VIH VIL IX Description Power Supply Voltage I/O Supply Voltage Output HIGH Voltage Output LOW Voltage Input HIGH Voltage[7] Input LOW Voltage[7] Input Load Current except ZZ and MODE VDDQ = 3.3V VDDQ = 2.5V Test Conditions Min. 3.135 3.135 2.375 2.4 2.0 Max. 3.6 VDD 2.625 Unit V V V V V VDDQ = 3.3V, VDD = Min., IOH = -4.0 mA VDDQ = 2.5V, VDD = Min., IOH= -1.0 mA VDDQ = 3.3V, VDD = Min., IOL = 8.0 mA VDDQ = 2.5V, VDD = Min., IOL = 1.0 mA VDDQ = 3.3V VDDQ = 2.5V VDDQ = 3.3V VDDQ = 2.5V GND VI VDDQ 0.4 0.4 2.0 1.7 -0.3 -0.3 -5 -30 5 -5 30 -5 5 250 220 180 50 VDD + 0.3V VDD + 0.3V 0.8 0.7 5 V V V V V V A A A A A A mA mA mA mA Input Current of MODE Input = VSS Input = VDD Input Current of ZZ IOZ IDD Input = VSS Input = VDD Output Leakage Current GND VI VDDQ, Output Disabled VDD Operating Supply Current Automatic CE Power-down Current--TTL Inputs VDD = Max., IOUT = 0 mA, f = fMAX = 1/tCYC VDD = Max, Device Deselected, VIN VIH or VIN VIL f = fMAX = 1/tCYC 4.4-ns cycle, 225 MHz 5-ns cycle, 200 MHz 6-ns cycle, 166 MHz ISB1 ISB2 ISB3 ISB4 All speeds Automatic CE VDD = Max, Device Deselected, Power-down VIN 0.3V or VIN > VDDQ - 0.3V, Current--CMOS Inputs f = 0 All speeds 30 mA Automatic CE VDD = Max, Device Deselected, or All speeds Power-down VIN 0.3V or VIN > VDDQ - 0.3V Current--CMOS Inputs f = fMAX = 1/tCYC VDD = Max, Device Deselected, Automatic CE All Speeds Power-down VIN VIH or VIN VIL, f = 0 Current--TTL Inputs 50 mA 40 mA Shaded areas contain advance information. Notes: 7. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2), undershoot: VIL(AC) > -2V (Pulse width less than tCYC/2). 8. TPower-up: Assumes a linear ramp from 0v to VDD(min.) within 200ms. During this time VIH < VDD and VDDQ < VDD\ Document #: 38-05542 Rev. *A Page 17 of 27 PRELIMINARY Thermal Resistance[9] Parameter Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. TQFP Package 25 9 BGA Package 25 6 CY7C1366C CY7C1367C fBGA Package 27 6 Unit C/W C/W JA JC Capacitance[9] Parameter CIN CCLK CI/O Description Input Capacitance Clock Input Capacitance Input/Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VDD = 3.3V. VDDQ = 2.5V TQFP Package 5 5 5 BGA Package 5 5 7 fBGA Package 5 5 7 Unit pF pF pF AC Test Loads and Waveforms 3.3V I/O Test Load OUTPUT Z0 = 50 3.3V OUTPUT RL = 50 R = 317 VDDQ 5 pF GND R = 351 10% ALL INPUT PULSES 90% 90% 10% 1ns VT = 1.5V 1ns 2.5V I/O Test Load OUTPUT Z0 = 50 (a) INCLUDING JIG AND SCOPE 2.5V OUTPUT RL = 50 (b) R = 1667 VDDQ (c) ALL INPUT PULSES 10% 90% 90% 10% 1ns 5 pF GND R =1538 VT = 1.25V 1ns (a) INCLUDING JIG AND SCOPE (b) (c) Note: 9. Tested initially and after any design or process change that may affect these parameters. Document #: 38-05542 Rev. *A Page 18 of 27 PRELIMINARY Switching Characteristics Over the Operating Range[14, 15] 225 MHz Parameter tPOWER Clock tCYC tCH tCL Output Times tCO tDOH tCLZ tCHZ tOEV tOELZ tOEHZ Set-up Times tAS tADS tADVS tWES tDS tCES Hold Times tAH tADH tADVH tWEH tDH tCEH Address Hold After CLK Rise ADSP , ADSC Hold After CLK Rise ADV Hold After CLK Rise GW,BWE, BWX Hold After CLK Rise Data Input Hold After CLK Rise Chip Enable Hold After CLK Rise 0.4 0.4 0.4 0.4 0.4 0.4 0.5 0.5 0.5 0.5 0.5 0.5 Address Set-up Before CLK Rise ADSC, ADSP Set-up Before CLK Rise ADV Set-up Before CLK Rise GW, BWE, BWX Set-up Before CLK Rise Data Input Set-up Before CLK Rise Chip Enable Set-Up Before CLK Rise 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.5 1.5 1.5 1.5 Data Output Valid After CLK Rise Data Output Hold After CLK Rise Clock to Low-Z[11, 12, 13] Clock to High-Z[11, 12, 13] OE LOW to Output Valid OE LOW to Output Low-Z[11, 12, 13] OE HIGH to Output High-Z [11, 12, 13] CY7C1366C CY7C1367C 200 MHz Min. 1 5.0 2.0 2.0 Max 166 MHz Min. 1 6.0 2.4 2.4 3.0 1.25 1.25 1.25 1.25 3.0 3.0 0 0 3.0 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 3.5 1.25 3.5 3.5 3.5 Max Unit ms ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Description VDD(Typical) to the first Access[10] Clock Cycle Time Clock HIGH Clock LOW Min. 1 4.4 1.8 1.8 Max 2.8 1.25 1.25 1.25 0 2.8 2.8 2.8 1.25 Shaded areas contain advance information. Notes: 10. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can be initiated. 11. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured 200 mV from steady-state voltage. 12. At any given voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve High-Z prior to Low-Z under the same system conditions 13. This parameter is sampled and not 100% tested. 14. Timing reference level is 1.5V when VDDQ = 3.3V and is 1.25V when VDDQ = 2.5V. 15. Test conditions shown in (a) of AC Test Loads unless otherwise noted. Document #: 38-05542 Rev. *A Page 19 of 27 PRELIMINARY Switching Waveforms Read Cycle Timing[16] tCYC CY7C1366C CY7C1367C CLK tCH tADS tADH tCL ADSP tADS tADH ADSC tAS tAH ADDRESS A1 tWES tWEH A2 A3 Burst continued with new base address GW, BWE,BW X tCES tCEH Deselect cycle CE tADVS tADVH ADV ADV suspends burst OE tOEV t CLZ t OEHZ t OELZ tCO tDOH t CHZ Data Out (DQ) High-Z Q(A1) t CO Q(A2) Q(A2 + 1) Q(A2 + 2) Q(A2 + 3) Q(A2) Q(A2 + 1) Q(A3) Single READ BURST READ Burst wraps around to its initial state DON'T CARE UNDEFINED Notes: 16. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH. Document #: 38-05542 Rev. *A Page 20 of 27 PRELIMINARY Switching Waveforms (continued) Write Cycle Timing[16, 17] t CYC CY7C1366C CY7C1367C CLK tCH tADS tADH tCL ADSP tADS tADH ADSC extends burst tADS tADH ADSC tAS tAH ADDRESS A1 A2 Byte write signals are ignored for first cycle when ADSP initiates burst A3 tWES tWEH BWE, BWX tWES tWEH GW tCES tCEH CE tADVS tADVH ADV ADV suspends burst OE t DS t DH Data in (D) High-Z t OEHZ D(A1) D(A2) D(A2 + 1) D(A2 + 1) D(A2 + 2) D(A2 + 3) D(A3) D(A3 + 1) D(A3 + 2) Data Out (Q) BURST READ Single WRITE BURST WRITE DON'T CARE UNDEFINED Extended BURST WRITE Note: 17. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW and BWX LOW. Document #: 38-05542 Rev. *A Page 21 of 27 PRELIMINARY Switching Waveforms (continued) Read/Write Cycle Timing[16, 18, 19] tCYC CY7C1366C CY7C1367C CLK tCH tADS tADH tCL ADSP ADSC tAS tAH ADDRESS BWE, BWX A1 A2 A3 tWES tWEH A4 A5 A6 tCES tCEH CE ADV OE tCO tDS tDH tOELZ Data In (D) Data Out (Q) High-Z tCLZ tOEHZ D(A3) D(A5) D(A6) High-Z Q(A1) Back-to-Back READs Q(A2) Single WRITE DON'T CARE Q(A4) Q(A4+1) BURST READ Q(A4+2) Q(A4+3) Back-to-Back WRITEs UNDEFINED Notes: 18. The data bus (Q) remains in high-Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC. 19. GW is HIGH. Document #: 38-05542 Rev. *A Page 22 of 27 PRELIMINARY Switching Waveforms (continued) ZZ Mode Timing [20, 21] CLK t ZZ t ZZREC CY7C1366C CY7C1367C ZZ t ZZI I SUPPLY I DDZZ t RZZI DESELECT or READ Only ALL INPUTS (except ZZ) Outputs (Q) High-Z DON'T CARE Ordering Information Speed (MHz) 225 Ordering Code CY7C1366C-225AXC CY7C1367C-225AXC CY7C1366C-225AXI CY7C1367C-225AXI CY7C1366C-225BGC CY7C1367C-225BGC CY7C1366C-225BGI CY7C1367C-225BGI CY7C1366C-225BZC CY7C1367C-225BZC CY7C1366C-225BZI CY7C1367C-225BZI 200 CY7C1366C-200AXC CY7C1367C-200AXC CY7C1366C-200AXI CY7C1367C-200AXI CY7C1366C-200BGC CY7C1367C-200BGC CY7C1366C-200BGI CY7C1367C-200BGI CY7C1366C-200BZC CY7C1367C-200BZC CY7C1366C-200BZI CY7C1367C-200BZI BB165D BB165D BG119 BG119 A101 A101 BB165D BB165D BG119 BG119 A101 Package Name A101 Part and Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Operating Range Commercial Industrial 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial JTAG 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables with JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial 3 Chip Enables with JTAG 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables Commercial Industrial 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Commercial JTAG 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with Industrial JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Commercial 3 Chip Enables with JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) Industrial 3 Chip Enables with JTAG Notes: 20. Device must be deselected when entering ZZ mode. See Cycle Descriptions table for all possible signal conditions to deselect the device. 21. DQs are in high-Z when exiting ZZ sleep mode. Document #: 38-05542 Rev. *A Page 23 of 27 PRELIMINARY Ordering Information (continued) Speed (MHz) 166 Ordering Code CY7C1366C-166AXC CY7C1367C-166AXC CY7C1366C-166AXI CY7C1367C-166AXI CY7C1366C-166BGC CY7C1367C-166BGC CY7C1366C-166BGI CY7C1367C-166BGI CY7C1366C-166BZC CY7C1367C-166BGC CY7C1366C-166BZI CY7C1367C-166BGI BB165D BB165D BG119 BG119 A101 Package Name A101 Part and Package Type 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables 100-lead Thin Quad Flat Pack (14 x 20 x 1.4mm) 3 Chip Enables CY7C1366C CY7C1367C Operating Range Commercial Industrial Commercial Industrial Commercial Industrial 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG 119-ball (14 x 22 x 2.4 mm) BGA 2 Chip Enables with JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables with JTAG 165-ball Fine-Pitch Ball Grid Array (13 x 15 x 1.4mm) 3 Chip Enables with JTAG Shaded areas contain advance information. Please contact your local sales representative for availability of these parts.Lead-free BG and BZ packages (Ordering code:BGX,BZX) will be available in 2005. Package Diagrams 100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101 16.000.20 14.000.10 100 1 81 80 DIMENSIONS ARE IN MILLIMETERS. 1.400.05 0.300.08 22.000.20 20.000.10 0.65 TYP. 30 31 50 51 121 (8X) SEE DETAIL A 0.20 MAX. 1.60 MAX. STAND-OFF 0.05 MIN. 0.15 MAX. 0.10 R 0.08 MIN. 0.20 MAX. 0 MIN. 0.25 GAUGE PLANE R 0.08 MIN. 0.20 MAX. SEATING PLANE 0-7 0.600.15 0.20 MIN. 1.00 REF. DETAIL A 51-85050-*A Document #: 38-05542 Rev. *A Page 24 of 27 PRELIMINARY Package Diagrams (continued) 119-Lead PBGA (14 x 22 x 2.4 mm) BG119 CY7C1366C CY7C1367C 51-85115-*B Document #: 38-05542 Rev. *A Page 25 of 27 PRELIMINARY Package Diagrams (continued) 165 FBGA 13 x 15 x 1.40 MM BB165D CY7C1366C CY7C1367C 51-85180-** i486 is a trademark, and Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark of IBM Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-05542 Rev. *A Page 26 of 27 (c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PRELIMINARY Document History Page CY7C1366C CY7C1367C Document Title: CY7C1366C/CY7C1367C 9-Mbit (256K x 36/512K x 18) Pipelined DCD Sync SRAM (Preliminary) Document Number: 38-05542 REV. ** *A ECN NO. 241690 278969 Issue Date See ECN See ECN Orig. of Change RKF RKF New data sheet Changed Boundary Scan order to match the B rev of these devices. Description of Change Document #: 38-05542 Rev. *A Page 27 of 27 |
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